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Cryptographic Hardware and Embedded Systems - CHES 2007
FPGA Intrinsic PUFs and Their Use for IP Protection
other
Author(s):
Jorge Guajardo
,
Sandeep S. Kumar
,
Geert-Jan Schrijen
,
Pim Tuyls
Publication date
(Print):
2007
Publisher:
Springer Berlin Heidelberg
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Book Chapter
Pages
: 63-80
DOI:
10.1007/978-3-540-74735-2_5
SO-VID:
ecd70092-2bd0-4260-8f0c-ee3a178513bd
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Book chapters
pp. 181
Secret External Encodings Do Not Prevent Transient Fault Analysis
pp. 272
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
pp. 28
Side Channel Cryptanalysis of a Higher Order Masking Scheme
pp. 45
High-Speed True Random Number Generation with Logic Gates Only
pp. 63
FPGA Intrinsic PUFs and Their Use for IP Protection
pp. 81
Evaluation of the Masked Logic Style MDPL on a Prototype Chip
pp. 121
On the Power of Bitslice Implementation on Intel Core2 Processor
pp. 148
MAME: A Compression Function with Reduced Hardware Requirements
pp. 209
AES Encryption Implementation and Analysis on Commodity Graphics Processing Units
pp. 427
Information Theoretic Evaluation of Side-Channel Resistant Logic Styles
pp. 450
PRESENT: An Ultra-Lightweight Block Cipher
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